B2.64 Id_Dfr0_El1, Aarch32 Debug Feature Register 0, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
The ID_DFR0_EL1 provides top-level information about the debug system in AArch32.
Bit field descriptions
ID_DFR0_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
RES0, [31:28]
PerfMon, [27:24]
MProfDbg, [23:20]
MMapTrc, [19:16]
CopTrc, [15:12]
RES0, [11:8]
CopSDbg, [7:4]
CopDbg, [3:0]
100798_0300_00_en
31 28 27 24 23
PerfMon
0
RES
Reserved.
RES0
Indicates support for performance monitor model:
Support for Performance Monitor Unit version 3 (PMUv3) system registers, with a
4
16-bit evtCount field.
Indicates support for memory-mapped debug model for M profile cores:
This product does not support M profile Debug architecture.
0
Indicates support for memory-mapped trace model:
Support for Arm trace architecture, with memory-mapped access.
1
In the Trace registers, the ETMIDR gives more information about the implementation.
Indicates support for coprocessor-based trace model:
This product does not support Arm trace architecture.
0
Reserved.
RES0
Indicates support for coprocessor-based Secure debug model:
This product supports the Armv8.2 Debug architecture.
8
Indicates support for coprocessor-based debug model:
This product supports the Armv8.2 Debug architecture.
8
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B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1

20 19 16 15
MProfDbg MMapTrc CopTrc
Figure B2-48 ID_DFR0_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
12 11 8 7 4 3
CopSDbg
0
CopDbg
B2-231