D6.3 Pmcidr0, Performance Monitors Component Identification Register 0 - ARM Cortex-A76 Core Technical Reference Manual

D6.3 PMCIDR0, Performance Monitors Component Identification Register 0
The PMCIDR0 provides information to identify a Performance Monitor component.
Bit field descriptions
The PMCIDR0 is a 32-bit register.
RES0, [31:8]
PRMBL_0, [7:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMCIDR0 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Preamble byte 0.
0x0D
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D6.3 PMCIDR0, Performance Monitors Component Identification Register 0

Figure D6-2 PMCIDR0 bit assignments
reserved.
Non-Confidential
D6 Memory-mapped PMU registers
8 7 0
PRMBL_0
®
.
0xFF0
D6-461