ARM Cortex-A76 Core Technical Reference Manual page 600

B.1 Revisions
This appendix describes the technical changes between released issues of this book
Change
Added support for 128KB L2 cache size.
Added note to indicate support for Dot Product
instructions introduced in the Armv8.4
Extension.
Updated BPIQ data location encoding table.
Updated replacement policy to dynamic biased
replacement policy.
Updated reset values for ID_AA64ISAR0_EL1,
IDAA64MMFR1_EL1, IDMMFR4_EL1, and
MIDR_EL1.
Updated CCSIDR_EL1 encodings table.
Updated CPUECTLR_EL1 register description.
Updated bits [43:32] of ID_AA64ISAR0_EL1
register.
Updated bits [15:12] of ID_AA64MMFR1_EL1
register.
Added ID_ISAR6_EL1 register.
Added Activity Monitor Unit chapter.
Updated reset value for TRCIDR1 register.
Updated bits [3:0] of TRCIDR1 register.
100798_0300_00_en
Table B-2 Differences between Issue 0000-00 and Issue 0100-00
Location
Throughout document
A1.1 About the core on page A1-26
A6.6.1 Encoding for L1 instruction cache tag, L1 instruction cache
data, L1 BTB, L1 GHB, L1 TLB instruction, and BPIQ
on page A6-80
A7.1 About the L2 memory system on page A7-98
B2.4 AArch64 registers by functional group on page B2-136
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 on page B2-159
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
on page B2-172
B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute
Register 0, EL1 on page B2-219
B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature
Register 1, EL1 on page B2-224
B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6,
EL1 on page B2-245
Chapter C3 Activity Monitor Unit on page C3-385
D9.1 ETM register summary on page D9-495
D9.30 TRCIDR1, ID Register 1 on page D9-536
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
B Revisions
B.1 Revisions
Table B-1 Issue 0000-00
Change Location Affects
First release - -
Affects
r1p0
r1p0
r1p0
r1p0
r1p0
r1p0
r1p0
r1p0
r1p0
r1p0
All versions
r1p0
r1p0
Appx-B-600