ARM Cortex-A76 Core Technical Reference Manual page 89

The following table shows the data that is returned from accessing the L2 tag RAM when L2 is
configured with a 128KB cache size.
100798_0300_00_en
Bit fields of Rd
[31:24]
[23:21]
[20:18]
[17:16]
[15:6]
[5:0]
Bit fields of Rd
[31:24]
[23:21]
[20:18]
[17:16]
[15:4]
[3:0]
Bit fields of Rd
[31:24]
[23:16]
[15:6]
[5:0]
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A6 Level 1 memory system
A6.6 Direct access to internal memory
Table A6-22 L2 tag location encoding
Description
RAMID = 0x10
Reserved
Way (0->7)
Reserved
Index[15:6]
Reserved
Table A6-23 L2 data location encoding
Description
RAMID = 0x11
Reserved
Way (0->7)
Reserved
Index[15:4]
Reserved
Table A6-24 L2 victim location encoding
Description
RAMID = 0x12
Reserved
Index[15:6]
Reserved
A6-89