D9.12
TRCCIDR2, ETM Component Identification Register 2
The TRCCIDR2 provides information to identify a CTI component.
Bit field descriptions
The TRCCIDR2 is a 32-bit register.
RES0, [31:8]
PRMBL_2, [7:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCIDR2 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Preamble byte 2.
0x05
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
D9.12 TRCCIDR2, ETM Component Identification Register 2
Figure D9-11 TRCCIDR2 bit assignments
reserved.
Non-Confidential
D9 ETM registers
8
7
0
PRMBL_2
®
.
0xFF8
D9-511
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