ARM Cortex-A76 Core Technical Reference Manual page 160

Associativity, [12:3]
LineSize, [2:0]
Configurations
CCSIDR_EL1 encodings
The following table shows the individual bit field and complete register encodings for the CCSIDR_EL1.
CSSELR Cache
Level InD
0b000 0b0
L1 Data cache
0b000 0b1
L1 Instruction
cache
0b001 0b0
L2 cache
0b001 0b1
Reserved
0b010 0b0
Reserved
0b010 0b1
Reserved
0b0101 - 0b1111 Reserved
100798_0300_00_en
(Associativity of cache) - 1. Therefore, a value of 0 indicates an associativity of 1. The
associativity does not have to be a power of 2.
For more information about encoding, see
(Log (Number of bytes in cache line)) - 4. For example:
2
Indicates the (log (number of words in cache line)) - 2:
2
For a line length of 16 bytes: Log
line length.
For a line length of 32 bytes: Log
For more information about encoding, see
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
®
Size Complete
register
encoding
701FE01A
64KB
201FE01A
64KB
128KB 701FE03A
256KB 703FE03A
512KB 707FE03A
- -
- -
- -
- -
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
CCSIDR_EL1 encodings on page
(16) = 4, LineSize entry = 0. This is the minimum
2
(32) = 5, LineSize entry = 1.
2
CCSIDR_EL1 encodings on page
Register bit field encoding
WT WB RA WA NumSets Associativity LineSize
0 1 1 1
0 0 1 0
0 1 1 1
0 1 1 1
0 1 1 1
- - - -
- - - -
- - - -
- - - -
reserved.
Non-Confidential
B2 AArch64 system registers
B2-160.
B2-160.
Table B2-6 CCSIDR encodings
0x00FF 0x003
0x00FF 0x003
0x00FF 0x007
0x01FF 0x007
0x03FF 0x007
- -
- -
- -
- -
2
2
2
2
2
-
-
-
-
B2-160