Table of Contents
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Chapter D9
ETM registers
This chapter describes the ETM registers.
It contains the following sections:
•
D9.1 ETM register summary on page
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D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7 on page
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D9.3 TRCACVRn, Address Comparator Value Registers 0-7 on page
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D9.4 TRCAUTHSTATUS, Authentication Status Register on page
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D9.5 TRCAUXCTLR, Auxiliary Control Register on page
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D9.6 TRCBBCTLR, Branch Broadcast Control Register on page
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D9.7 TRCCCCTLR, Cycle Count Control Register on page
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D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0 on page
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D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0 on page
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D9.10 TRCCIDR0, ETM Component Identification Register 0 on page
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D9.11 TRCCIDR1, ETM Component Identification Register 1 on page
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D9.12 TRCCIDR2, ETM Component Identification Register 2 on page
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D9.13 TRCCIDR3, ETM Component Identification Register 3 on page
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D9.14 TRCCLAIMCLR, Claim Tag Clear Register on page
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D9.15 TRCCLAIMSET, Claim Tag Set Register on page
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D9.16 TRCCNTCTLR0, Counter Control Register 0 on page
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D9.17 TRCCNTCTLR1, Counter Control Register 1 on page
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D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1 on page
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D9.19 TRCCNTVRn, Counter Value Registers 0-1 on page
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D9.20 TRCCONFIGR, Trace Configuration Register on page
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D9.21 TRCDEVAFF0, Device Affinity Register 0 on page
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D9.22 TRCDEVAFF1, Device Affinity Register 1 on page
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D9.23 TRCDEVARCH, Device Architecture Register on page
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