D6.4 Pmcidr1, Performance Monitors Component Identification Register 1 - ARM Cortex-A76 Core Technical Reference Manual

D6.4 PMCIDR1, Performance Monitors Component Identification Register 1
The PMCIDR1 provides information to identify a Performance Monitor component.
Bit field descriptions
The PMCIDR1 is a 32-bit register.
RES0, [31:8]
CLASS, [7:4]
PRMBL_1, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMCIDR1 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Debug component.
0x9
Preamble byte 1.
0x0
Copyright © 2016–2018 Arm Limited or its affiliates. All rights

D6.4 PMCIDR1, Performance Monitors Component Identification Register 1

Figure D6-3 PMCIDR1 bit assignments
reserved.
Non-Confidential
D6 Memory-mapped PMU registers
8 7 4 3 0
CLASS PRMBL_1
®
.
0xFF4
D6-462