ARM Cortex-A76 Core Technical Reference Manual page 448

D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register
0, EL0
The PMCEID0_EL0 defines which common architectural and common microarchitectural feature events
are implemented.
Bit field descriptions
ID[31:0], [31:0]
Bit Event mnemonic
[31] L1D_CACHE_ALLOCATE
[30] CHAIN
[29] BUS_CYCLES
[28] TTBR_WRITE_RETIRED
[27] INST_SPEC
[26] MEMORY_ERROR
[25] BUS_ACCESS
[24] L2D_CACHE_WB
100798_0300_00_en
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Common architectural and microarchitectural feature events that can be counted by the PMU
event counters.
For each bit described in the following table, the event is implemented if the bit is set to 1, or
not implemented if the bit is set to 0.
Description
L1 Data cache allocate:
0 This event is not implemented.
Chain. For odd-numbered counters, counts once for each overflow of the preceding even-
numbered counter. For even-numbered counters, does not count:
1 This event is implemented.
Bus cycle:
This event is implemented.
1
TTBR write, architecturally executed, condition check pass - write to translation table base:
1 This event is implemented.
Instruction speculatively executed:
1 This event is implemented.
Local memory error:
1 This event is implemented.
Bus access:
1 This event is implemented.
L2 Data cache Write-Back:
1 This event is implemented.
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16 15 14 13
ID[31:0]
Figure D5-1 PMCEID0_EL0 bit assignments
reserved.
Non-Confidential
D5 AArch64 PMU registers
12 11 10 9 8 7 6 5 4 3
Table D5-2 PMU common events
2 1 0
D5-448