D9.29 Trcidr0, Id Register 0 - ARM Cortex-A76 Core Technical Reference Manual

D9.29 TRCIDR0, ID Register 0
The TRCIDR0 returns the tracing capabilities of the ETM trace unit.
Bit field descriptions
The TRCIDR0 is a 32-bit register.
31 30 29 28
1
RES
0
RES
RES0, [31:30]
COMMOPT, [29]
TSSIZE, [28:24]
RES0, [23:17]
QSUPP, [16:15]
QFILT, [14]
CONDTYPE, [13:12]
NUMEVENT, [11:10]
RETSTACK, [9]
100798_0300_00_en
24 23
TSSIZE
COMMOPT
CONDTYPE
NUMEVENT
RETSTACK
Reserved.
RES0
Indicates the meaning of the commit field in some packets:
Commit mode 1.
1
Global timestamp size field:
Implementation supports a maximum global timestamp of 64 bits.
0b01000
Reserved.
RES0
Indicates Q element support:
Q elements not supported.
0b00
Indicates Q element filtering support:
Q element filtering not supported.
0b0
Indicates how conditional results are traced:
Conditional trace not supported.
0b00
Number of events supported in the trace, minus 1:
Four events supported.
0b11
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
17 16 15 14 13 12 11 10 9 8 7 6
QSUPP
QFILT
Figure D9-27 TRCIDR0 bit assignments
reserved.
Non-Confidential
D9 ETM registers

D9.29 TRCIDR0, ID Register 0

5 4 3 2 1 0
INSTP0
TRCDATA
TRCBB
TRCCOND
TRCCCI
D9-534