A1.7 Product Revisions - ARM Cortex-A76 Core Technical Reference Manual

A1.7 Product revisions
This section indicates the first release and, in subsequent releases, describes the differences in
functionality between product revisions.
r0p0
r1p0
r2p0
r3p0
100798_0300_00_en
First release.
Further development and optimization of the product, including updates to the L2 data RAM
control inputs to allow multi-cycle hold timing constraints to ease timing closure.
Includes Inter-Exception level isolation of branch predictor structures so that an Exception
Level cannot train branch prediction for a different Exception Level to reliability hit in these
trained prediction entries. Implemented new barrier SSBB.
Implemented new barriers PSSBB and CSDB. Support for Speculative Store Bypass Safe
(SSBS) bit enabling software to indicate whether hardware is permitted to load or store
speculatively.
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A1 Introduction

A1.7 Product revisions

A1-32