D9.50 Trcoslar, Os Lock Access Register - ARM Cortex-A76 Core Technical Reference Manual

D9.50 TRCOSLAR, OS Lock Access Register
The TRCOSLAR sets and clears the OS Lock, to lock out external debugger accesses to the ETM trace
unit registers.
Bit field descriptions
The TRCOSLAR is a 32-bit register.
RES0, [31:1]
OSLK, [0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCOSLAR can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
OS Lock key value:
Unlock the OS Lock.
0
Lock the OS Lock.
1
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
Figure D9-48 TRCOSLAR bit assignments
reserved.
Non-Confidential
D9 ETM registers

D9.50 TRCOSLAR, OS Lock Access Register

.
0x300
1 0
OSLK
®
D9-560