ARM Cortex-A76 Core Technical Reference Manual page 228

AdvSIMD, [23:20]
FP, [19:16]
EL3 handling, [15:12]
EL2 handling, [11:8]
EL1 handling, [7:4]
EL0 handling, [3:0]
Configurations
100798_0300_00_en
Advanced SIMD. The possible values are:
Advanced SIMD, including Half-precision support, is implemented.
0x1
Floating-point. The possible values are:
Floating-point, including Half-precision support, is implemented.
0x1
EL3 exception handling:
Instructions can be executed at EL3 in AArch64 state only.
0x1
EL2 exception handling:
Instructions can be executed at EL3 in AArch64 state only.
0x1
EL1 exception handling. The possible values are:
Instructions can be executed at EL3 in AArch64 state only.
0x1
EL0 exception handling. The possible values are:
Instructions can be executed at EL0 in AArch64 or AArch32 state.
0x2
ID_AA64PFR0_EL1 is architecturally mapped to External register EDPFR.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
reserved.
Non-Confidential
B2 AArch64 system registers
B2-228