ARM Cortex-A76 Core Technical Reference Manual page 91

Register
Data Register 0
Data Register 1
Data Register 2
The following table shows the data that is returned from accessing the L2 tag RAM when L2 is
configured with a 512KB cache size.
100798_0300_00_en
Bit field
[63:44]
[43:37]
[36:12]
[11]
[10:9]
[8:6]
[5]
[4]
[3]
[2:0]
[63:0]
[63:0]
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A6.6 Direct access to internal memory
Table A6-26 L2 tag format with a 256KB L2 cache size
Description
0
ECC [6:0] if configured with ECC for a
256KB L2 cache size, otherwise 0
Physical address [39:15]
Non-secure identifier for the physical
address
Virtual index [13:12]
Reserved
Shareable
Outer allocation hint
L1 data cache valid
L2 State
101
001
x11
xx0
0
0
A6 Level 1 memory system
Modified
Exclusive
Shared
Invalid
A6-91