B2.62 Id_Aa64Pfr1_El1, Aarch64 Processor Feature Register 1, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
The ID_AA64PFR1_EL1 provides additional information about implemented core features in AArch64.
Bit field descriptions
ID_AA64PFR1_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
63
0
RES
RES0, [63:8]
SSBS, [7:4]
RES0, [3:0]
Configurations
100798_0300_00_en
Reserved.
RES0
PSTATE.SSBS. The possible values are:
AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative
0x1
Store Bypassing Safe (SSBS), but does not implement the MSR/MRS instructions to
directly read and write the PSTATE.SSBS field.
Reserved.
RES0
ID_AA64PFR1_EL1 is architecturally mapped to External register EDPFR.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1

Figure B2-46 ID_AA64PFR1_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
8 7 4 3 0
SSBS
B2-229