ARM Cortex-A76 Core Technical Reference Manual page 174

HPA_CAP, [48]
HPA_L1_DIS, [47]
HPA_DIS, [46]
RES0, [45:44]
L2_FLUSH, [43]
RES0, [42]
PFT_MM, [41:40]
100798_0300_00_en
Moderately conservative hardware page aggregation. This is the reset value.
00
Aggressive hardware page aggregation.
01
Moderately aggressive hardware page aggregation.
10
Conservative hardware page aggregation.
11
Limited or full hardware page aggregation selection . The possible values are:
Limited hardware page aggregation. This is the reset value.
0
Full hardware page aggregation.
1
Disables HPA in L1 TLBs (but continues to use HPA in L2 TLB). The possible values are:
Enables hardware page aggregation in L1 TLBs. This is the reset value.
0
Disables hardware page aggregation in L1 TLBs.
1
Disables hardware page aggregation. The possible values are:
Enables hardware page aggregation. This is the reset value.
0
Disables hardware page aggregation.
1
Reserved.
RES0
Allocation behavior of copybacks caused by L2 cache hardware flush and DC CISW
instructions targeting the L2 cache. If it is known that data is likely to be used soon by another
core, setting this bit can improve system performance. The possible values are:
L2 cache flushes and invalidates by set/way do not allocate in the L3 cache. Cache
0
lines in the UniqueDirty state cause WriteBack transactions with the allocation hint
cleared, while cache lines in UniqueClean or SharedClean states cause address-only
Evict transactions. This is the reset value.
L2 cache flushes by set/way allocate in the L3 cache. Cache lines in the UniqueDirty
1
or UniqueClean state cause WriteBackFull or WriteEvictFull transactions,
respectively, both with the allocation hint set. Cache lines in the SharedClean state
cause address-only Evict transactions.
Reserved.
RES0
DRAM prefetch using PrefetchTgt transactions for table walk requests. The possible values are:
Disable prefetchtgt generation for requests from the Memory Management unit
00
(MMU). This is the reset value.
Conservatively generate prefetchtgt for cacheable requests from the MMU, always
01
generate for non-cacheable.
Aggressively generate prefetchtgt for cacheable requests from the MMU, always
10
generate for non-cacheable.
Always generate prefetchtgt for cacheable requests from the MMU, always generate
11
for non-cacheable.
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B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
reserved.
Non-Confidential
B2 AArch64 system registers
B2-174