Cache Protection Behavior - ARM Cortex-A76 Core Technical Reference Manual

A8.2

Cache protection behavior

The configuration of the RAS extension that is implemented in the Cortex-A76 core includes cache
protection.
In this case, the Cortex-A76 core protects against errors that result in a RAM bitcell holding the incorrect
value.
The RAMs in the Cortex-A76 core have the following capability:
SED
Interleaved parity
SECDED
Table A8-1 Cache protection behavior on page A8-103
each RAM.
The core can progress and remain functionally correct when there is a single bit error in any RAM.
If there are multiple single bit errors in different RAMs, or within different protection granules within the
same RAM, then the core also remains functionally correct.
If there is a double bit error in a single RAM within the same protection granule, then the behavior
depends on the RAM:
• For RAMs with SECDED capability, the core detects and either reports or defers the error. If the error
is in a cache line containing dirty data, then that data might be lost.
• For RAMs with only SED, the core does not detect a double bit error. This might cause data
corruption.
If there are three or more bit errors within the same protection granule, then depending on the RAM and
the position of the errors within the RAM, the core might or might not detect the errors.
The cache protection feature of the core has a minimal performance impact when no errors are present.
RAM
L1 instruction cache tag
L1 instruction cache data
L1 BTB
L1 GHB
L1 BPIQ
L1 data cache tag
100798_0300_00_en
Single Error Detect. One bit of parity is applicable to the entire word. The word size is specific
for each RAM and depends on the protection granule.
One bit of parity is applicable to the even bits of the word, and one bit of parity is applicable to
the odd bits of the word.
Single Error Correct, Double Error Detect.
Protection type Protection granule
1 parity bit 31 bits
SED 72 bits
None -
None -
None -
SECDED 34 bits + 7 bits for ECC attached to
the word.
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A8 Reliability, Availability, and Serviceability (RAS)
indicates which protection type is applied to
Correction behavior
The line that contains the error is invalidated
from the L1 instruction cache and fetched
again from the subsequent memory system.
The line that contains the error is invalidated
from the L1 instruction cache and fetched
again from the subsequent memory system.
-
-
-
The cache line that contains the error gets
evicted, corrected in line, and refilled to the
core.
reserved.
Non-Confidential
A8.2 Cache protection behavior
Table A8-1 Cache protection behavior
A8-103