ARM Cortex-A76 Core Technical Reference Manual page 596

Scenario
Accessing reserved debug registers
Clearing the clear-after-read EDPRSR bits when
Core power domain is on, and
DoubleLockStatus() is TRUE
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Table A-1 Armv8 Debug UNPREDICTABLE behaviors (continued)
Behavior
The core deviates from preferred behavior because the hardware cost to decode
some of these addresses in debug power domain is significantly high.
The actual behavior is:
1. For reserved debug registers in the address range 0x000-0xCFC and
Performance Monitors registers in the address range 0x000, the response is
either
CONSTRAINED UNPREDICTABLE
errors occurs:
Off
The core power domain is either completely off or in a low-power
state where the core power domain registers cannot be accessed.
DLK
DoubleLockStatus() is TRUE and OS double-lock is locked
(EDPRSR.DLK is 1).
OSLK
OS lock is locked (OSLSR_EL1.OSLK is 1).
2. For reserved debug registers in the address ranges 0x400-0x4FC and
0x800-0x8FC, the response is
when the conditions in
EDAD
AllowExternalDebugAccess() is FALSE. External debug
access is disabled.
3. For reserved Performance Monitor registers in the address ranges
0x000-0x0FC and 0x400-0x47C, the response is either
UNPREDICTABLE
and the following error occurs:
EPMAD
AllowExternalPMUAccess() is FALSE. External Performance
Monitors access is disabled.
The core behaves as indicated in the sole Preference:
• Bits are not cleared to zero.
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A Cortex -A76 Core AArch32 unpredictable behaviors
®
A.3 Armv8 Debug UNPREDICTABLE behaviors
Error or
RES0
CONSTRAINED UNPREDICTABLE
1 do not apply and the following error occurs:
Error, or when the conditions in
RES0
when any of the following
Error or
RES0
CONSTRAINED
1 and 2 do not apply,
Appx-A-596