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The following table shows the data that is returned from accessing the BPIQ RAM.
Register
Instruction Register 0
Instruction Register 1
Instruction Register 2
A6.6.2
Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data
The core data cache consists of a 4-way set-associative structure.
The encoding, which is set in
entry for tag, data, and TLB memory is shown in the following tables. It is similar for both the tag RAM,
data RAM, and TLB access. Data RAM access includes an additional field to locate the appropriate
doubleword in the cache line.
Tag RAM encoding includes an additional field to select which one of the two cache channels must be
used to perform any access.
100798_0300_00_en
Bit field
[63:0]
[63:32]
[31:0]
[63:0]
in the appropriate
Rd
Bit fields of Rd
[31:24]
[23:20]
[19:18]
[17]
[16:14]
[13:6]
[5:0]
Bit fields of Rd
[31:24]
[23:20]
[19:18]
[17:16]
[15:14]
[13:6]
[5:0]
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A6.6 Direct access to internal memory
Table A6-13 BPIQ cache format
Description
Data [63:0]
0
Data [95:64]
0
instruction, used to locate the required cache data
MCR
Table A6-14 L1 data cache tag location encoding
Description
RAMID = 0x08
Reserved
Way
Copy
0
Tag RAM associated with Pipe 0
1
Tag RAM associated with Pipe 1
Reserved
Index [13:6]
Reserved
Table A6-15 L1 data cache data location encoding
Description
RAMID = 0x09
Reserved
Way
BankSel
Unused
Index [13:6]
Reserved
A6 Level 1 memory system
A6-85
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