ARM Cortex-A76 Core Technical Reference Manual page 535

RES0, [8]
TRCCCI, [7]
TRCCOND, [6]
TRCBB, [5]
TRCDATA, [4:3]
INSTP0, [2:1]
RES1, [0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIDR0 can be accessed through the external debug interface, offset
100798_0300_00_en
Return stack support:
Return stack implemented.
1
Reserved.
RES0
Support for cycle counting in the instruction trace:
Cycle counting in the instruction trace is implemented.
1
Support for conditional instruction tracing:
Conditional instruction tracing is not supported.
0
Support for branch broadcast tracing:
Branch broadcast tracing is implemented.
1
Conditional tracing field:
Tracing of data addresses and data values is not implemented.
0b00
P0 tracing support field:
Tracing of load and store instructions as P0 elements is not supported.
0b00
Reserved.
RES1
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Non-Confidential
D9 ETM registers
D9.29 TRCIDR0, ID Register 0
®
.
0x1E0
D9-535