ARM Cortex-A76 Core Technical Reference Manual page 240

Saturate, [3:0]
Configurations
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
100798_0300_00_en
• The and
0x3 SSAT
• The ,
PKHBT PKHTB
, ,
SASX SEL SHADD16
, ,
SSUB8 SSAX SXTAB16
,
UHSUB16 UHSUB8
,
USAD8 USADA8
the GE[3:0] bits in the PSRs.
The SIMD field relates only to implemented instructions that perform SIMD
operations on the general-purpose registers. In an implementation that supports
Advanced SIMD and floating-point instructions, MVFR0, MVFR1, and MVFR2 give
information about the implemented Advanced SIMD instructions.
Indicates the implemented Saturate instructions:
The , ,
0x1 QADD QDADD
In an AArch64-only implementation, this register is
Must be interpreted with ID_ISAR0_EL1, ID_ISAR1_EL1, ID_ISAR2_EL1, ID_ISAR4_EL1,
ID_ISAR5_EL1, and ID_ISAR6_EL1. See:
• B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 on page
• B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 on page
• B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 on page
• B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 on page
• B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 on page
• B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 on page
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B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
instructions, and the Q bit in the PSRs.
USAT
, , , ,
QADD16 QADD8 QASX
, , ,
SHADD8 SHASX SHSUB16
, , ,
SXTB16 UADD16
, , ,
UHSAX UQADD16 UQADD8
, , , ,
USAT16 USUB16 USUB8
, Q bit in the PSRs.
QDSUB QSUB
UNKNOWN
reserved.
Non-Confidential
B2 AArch64 system registers
, , ,
QSUB16 QSUB8 QSAX SADD16
, , ,
SHSUB8 SHSAX SSAT16
, , ,
UADD8 UASX UHADD16 UHADD8
, , ,
UQASX UQSUB16 UQSUB8
, , instructions, and
USAX UXTAB16 UXTB16
.
, ,
SADD8
, ,
SSUB16
, ,
UHASX
, ,
UQSAX
B2-233.
B2-235.
B2-237.
B2-241.
B2-243.
B2-245.
®
B2-240