ARM Cortex-A76 Core Technical Reference Manual page 309

Configurations
100798_0300_00_en
There are no configuration notes.
ERR0STATUS resets to
0x00000000
ERR0STATUS is accessible from the following registers when ERRSELR.SEL==0:
• B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
on page B2-207.
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B3.10 ERR0STATUS, Error Record Primary Status Register
.
reserved.
Non-Confidential
B3 Error system registers
B3-309