ARM Cortex-A76 Core Technical Reference Manual page 204

B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control
Register, EL1
Register ERXPFGCTLR_EL1 accesses the ERR<n>PFGCTLR register for the error record selected by
ERRSELR_EL1.SEL.
If ERRSELR_EL1.SEL==0, then ERXPFGCTLR_EL1 accesses the ERR0PFGCTLR register of the core
error record. See
on page B3-303.
If ERRSELR_EL1.SEL==1, then ERXPFGCTLR_EL1 accesses the ERR1PFGCTLR register of the
DSU error record. See the Arm
Configurations
Accessing the ERXPFGCTLR_EL1
This syntax is encoded with the following settings in the instruction encoding:
Accessibility
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.
100798_0300_00_en
B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
DynamIQ
®
There are no configuration notes.
This register can be read using MRS with the following syntax:
MRS <syntax>
This register can be written using MSR with the following syntax:
MSR <syntax>
This register is accessible in software as follows:
<syntax>
S3_0_C15_C2_1
S3_0_C15_C2_1
S3_0_C15_C2_1
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Shared Unit Technical Reference Manual.
™
<systemreg>
S3_0_C15_C2_1 11
Control
E2H TGE
x x
x 0
x 1
reserved.
Non-Confidential
B2 AArch64 system registers
op0 op1 CRn CRm op2
000 1111 0010
Accessibility
NS EL0 EL1 EL2
0 - RW n/a
1 - RW RW
1 - n/a RW
001
EL3
RW
RW
RW
B2-204