D9.5 Trcauxctlr, Auxiliary Control Register - ARM Cortex-A76 Core Technical Reference Manual

D9.5 TRCAUXCTLR, Auxiliary Control Register
The TRCAUXCTLR provides
Bit field descriptions
RES0, [31:8]
CIFOVERRIDE, [7]
INOVFLOWEN, [6]
FLUSHOVERRIDE, [5]
TSIOVERRIDE, [4]
SYNCOVERRIDE, [3]
100798_0300_00_en
IMPLEMENTATION DEFINED
31
0
RES
Reserved.
RES0
Override core interface register repeater clock enable. The possible values are:
Core interface clock gate is enabled.
0
Core interface clock gate is disabled.
1
Allow overflows of the core interface buffer, removing any rare impact that the trace unit might
have on the core's speculation when enabled. The possible values are:
Core interface buffer overflows are disabled.
0
Core interface buffer overflows are enabled.
1
When this bit is set to 1, the trace start/stop logic might deviate from architecturally-specified
behavior.
Override ETM flush behavior. The possible values are:
ETM trace unit FIFO is flushed and ETM trace unit enters idle state when DBGEN or
0
NIDEN is LOW.
ETM trace unit FIFO is not flushed and ETM trace unit does not enter idle state when
1
DBGEN or NIDEN is LOW.
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.
Override TS packet insertion behavior. The possible values are:
Timestamp packets are inserted into FIFO only when trace activity is LOW.
0
Timestamp packets are inserted into FIFO irrespective of trace activity.
1
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D9.5 TRCAUXCTLR, Auxiliary Control Register

configuration and control options.
FLUSHOVERRIDE
SYNCOVERRIDE
FRSYNCOVFLOW
IDLEACKOVERRIDE
AFREADYOVERRIDE
Figure D9-4 TRCAUXCTLR bit assignments
reserved.
Non-Confidential
D9 ETM registers
8 7 6 5 4 3 2 1
CIFOVERRIDE
INOVFLOWEN
TSIOVERRIDE
0
D9-503