D7.9 Pmsscr, Pmu Snapshot Capture Register - ARM Cortex-A76 Core Technical Reference Manual

D7.9 PMSSCR, PMU Snapshot Capture Register
The PMSSCR provides a mechanism for software to initiate a sample.
Bit field descriptions
The PMSSCR is a 32-bit write-only register.
RES0, [31:1]
SS, [0]
Configurations
Usage constraints
Any access to PMSSCR returns an error if any of the following occurs:
• The core power domain is off.
• DoubleLockStatus() == TRUE.
100798_0300_00_en
31
0
RES
Reserved, .
RES0
Capture now. The possible values are:
0 Ignored.
1 Initiate a capture immediately.
There are no configuration notes.
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D7 PMU snapshot registers
Figure D7-3 PMSSCR bit assignments
0
1
SS
D7-480