ARM Cortex-A76 Core Technical Reference Manual page 327

Bit fields and details that are not provided in this description are architecturally defined. See the Arm
Generic Interrupt Controller Architecture Specification.
100798_0300_00_en
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU
interface.
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B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
reserved.
Non-Confidential
B4 GIC registers
®
B4-327