ARM Cortex-A76 Core Technical Reference Manual page 146

RES0, [6]
ERXPFGEN, [5]
AMEN, [4]
RES0, [3:2]
ECTLREN, [1]
Configurations
100798_0300_00_en
Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN,
0
CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are not write-
accessible from EL1 Non-secure. This is the reset value.
Registers CPUPWRCTLR, CLUSTERPWRCTLR, CLUSTERPWRDN,
1
CLUSTERPWRSTAT, CLUSTERL3HIT and CLUSTERL3MISS are write-accessible
from EL1 Non-secure if they are write-accessible from EL2.
Reserved.
RES0
Error Record Registers enable. The possible values are:
ERXPFG* are not write-accessible from EL1 Non-secure. This is the reset value.
0
ERXPFG* are write-accessible from EL1 Non-secure if they are write-accessible from
1
EL2.
Activity Monitor enable. The possible values are:
Non-secure accesses from EL1 and EL0 to activity monitor registers are trapped to
0
EL2.
Non-secure accesses from EL1 and EL0 to activity monitor registers are not trapped to
1
EL2.
Reserved.
RES0
Extended Control Registers enable. The possible values are:
CPUECTLR and CLUSTERECTLR are not write-accessible from EL1 Non-secure.
0
This is the reset value.
CPUECTLR and CLUSTERECTLR are write-accessible from EL1 Non-secure if they
1
are write-accessible from EL2.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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B2.6 ACTLR_EL2, Auxiliary Control Register, EL2
reserved.
Non-Confidential
B2 AArch64 system registers
B2-146