B2.68 Id_Isar3_El1, Aarch32 Instruction Set Attribute Register 3, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
The ID_ISAR3_EL1 provides information about the instruction sets implemented by the core in
AArch32.
Bit field descriptions
ID_ISAR3_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
T32EE, [31:28]
TrueNOP, [27:24]
T32Copy, [23:20]
TabBranch, [19:16]
SynchPrim, [15:12]
SVC, [11:8]
SIMD, [7:4]
100798_0300_00_en
31 28 27 24 23
T32EE TrueNOP
Indicates the implemented T32EE instructions:
None implemented.
0x0
Indicates support for True NOP instructions:
True instructions in both the A32 and T32 instruction sets, and additional NOP-
0x1 NOP
compatible hints.
Indicates the support for T32 non flag-setting
Support for T32 instruction set encoding T1 of the
0x1
from a low register to a low register.
Indicates the implemented Table Branch instructions in the T32 instruction set.
The and instructions.
0x1 TBB TBH
Indicates the implemented Synchronization Primitive instructions:
• The and
0x2 LDREX
• The ,
CLREX LDREXB
• The and
LDREXD
Indicates the implemented SVC instructions:
The instruction.
0x1 SVC
Indicates the implemented Single Instruction Multiple Data (SIMD) instructions.
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B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1

20 19 16 15
T32Copy SynchPrim
TabBranch
Figure B2-52 ID_ISAR3_EL1 bit assignments
instructions:
MOV
instructions.
STREX
, , and
STREXB STREXH
instructions.
STREXD
reserved.
Non-Confidential
B2 AArch64 system registers
12 11 8 7 4 3
SVC SIMD
(register) instruction, copying
MOV
instructions.
0
Saturate
B2-239