B3.7 Err0Pfgcdnr, Error Pseudo Fault Generation Count Down Register - ARM Cortex-A76 Core Technical Reference Manual

B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
ERR0PFGCDNR is the Cortex-A76 node register that generates one of the errors that are enabled in the
corresponding ERR0PFGCTL register.
Bit field descriptions
ERR0PFGCDNR is a 32-bit register and is RW.
CDN, [31:0]
Configurations
100798_0300_00_en
31
Count Down value. The reset value of the Error Generation Counter is used for the countdown.
There are no configuration options.
ERR0PFGCDNR resets to
When ERRSELR.SEL==0, ERR0PFGCDNR is accessible from
Selected Error Pseudo Fault Generation Count Down Register, EL1 on page
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B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register

CDN
Figure B3-5 ERR0PFGCDNR bit assignments
.
UNKNOWN
reserved.
Non-Confidential
B3 Error system registers
B2.43 ERXPFGCDNR_EL1,
B2-203.
B3-302
0