ARM Cortex-A76 Core Technical Reference Manual page 404

D1.1 AArch32 debug register summary
The following table summarizes the 32-bit and 64-bit debug control registers that are accessible in the
AArch32 Execution state from the internal CP14 interface. These registers are accessed by the
instructions in the order of CRn, op2, CRm, Op1 or
MRC
Op1.
For those registers not described in this chapter, see the Arm
Arm v8-A architecture profile.
®
CRn Op2 CRm Op1 Name
c0 0 c1
c0 0 c5
c0 0 c5
100798_0300_00_en
Type Reset
0 DBGDSCRint RO
0 DBGDTRTXint WO
0 DBGDTRRXint RO
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MCRR MRRC
Architecture Reference Manual Arm
®
Table D1-1 AArch32 debug register summary
Description
000x0000
Debug Status and Control Register, Internal View
- Debug Data Transfer Register, Transmit, Internal View
0x00000000 Debug Data Transfer Register, Receive, Internal View
reserved.
D1 AArch32 debug registers
D1.1 AArch32 debug register summary
MCR
instructions in the order of CRm,
and
v8, for
®
D1-404