ARM Cortex-A76 Core Technical Reference Manual page 83

Register
Instruction Register 0
Instruction Register 1
Instruction Register 2
The following table shows the data that is returned from accessing the L1 instruction TLB RAM.
100798_0300_00_en
Bit field
[63:0]
[63:32]
[31:0]
[63:0]
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A6 Level 1 memory system
A6.6 Direct access to internal memory
Table A6-11 L1 GHB cache format
Description
Data [63:0]
0
Data [95:64]
0
A6-83