ARM Cortex-A76 Core Technical Reference Manual page 418

Offset Name
0x81C
-
0x820
DBGWVR2_EL1[31:0]
0x824
DBGWVR2_EL1[63:32]
0x828
DBGWCR2_EL1
0x82C
-
0x830
DBGWVR3_EL1[31:0]
0x834
DBGWVR3_EL1[63:32]
0x838
DBGWCR3_EL1
0x83C-0xCFC -
0xD00
MIDR
0xD04-0xD1C -
0xD20
EDPFR[31:0]
0xD24
EDPFR[63:32]
0xD28
EDDFR[31:0]
0xD2C
EDDFR[63:32]
0xD60-0xEFC -
0xF00 -
0xF04-0xF9C -
0xFA0
DBGCLAIMSET_EL1
0xFA4
DBGCLAIMCLR_EL1
0xFA8
EDDEVAFF0
0xFAC
EDDEVAFF1
0xFB0
-
0xFB4
-
0xFB8
DBGAUTHSTATUS_EL1 RO
0xFBC
EDDEVARCH
0xFC0
EDDEVID2
0xFC4
EDDEVID1
0xFC8
EDDEVID
0xFCC
EDDEVTYPE
0xFD0
EDPIDR4
100798_0300_00_en
Table D3-1 Memory-mapped debug register summary (continued)
Type Width Description
- - Reserved
RW 64 Debug Watchpoint Value Register 2
RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
- - Reserved
RW 64 Debug Watchpoint Value Register 0,
RW 32 D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
on page D2-412
- - Reserved
RO 32 B2.84 MIDR_EL1, Main ID Register, EL1 on page B2-266
- - Reserved
RO 64 B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
on page B2-227
RO 64 B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
on page B2-227
- - Reserved
- - Reserved
- - Reserved
RW 32 D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
on page D2-411
RW 32 Debug Claim Tag Clear Register
RO 32
External Debug Device Affinity Register 0
RO 32 External Debug Device Affinity Register 1
- -
Reserved
- - Reserved
32
Debug Authentication Status Register
RO 32 External Debug Device Architecture Register
RO 32 External Debug Device ID Register 2,
RO 32 D3.7 EDDEVID1, External Debug Device ID Register 1 on page D3-425
RO 32 D3.6 EDDEVID, External Debug Device ID Register 0 on page D3-424
RO 32
External Debug Device Type Register
RO 32 D3.12 EDPIDR4, External Debug Peripheral Identification Register 4
on page D3-430
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D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
RES0
D3-418