D9.18 Trccntrldvrn, Counter Reload Value Registers 0-1 - ARM Cortex-A76 Core Technical Reference Manual

D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
The TRCCNTRLDVRn define the reload value for the counter.
Bit field descriptions
The TRCCNTRLDVRn is a 32-bit register.
RES0, [31:16]
VALUE, [15:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCCNTRLDVRn registers can be accessed through the external debug interface, offsets:
TRCCNTRLDVR0
TRCCNTRLDVR1
100798_0300_00_en
31
0
RES
Reserved.
RES0
Defines the reload value for the counter. This value is loaded into the counter each time the
reload event occurs.
.
0x140
.
0x144
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D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1

16 15
Figure D9-17 TRCCNTRLDVRn bit assignments
reserved.
Non-Confidential
D9 ETM registers
0
VALUE
®
D9-519