ARM Cortex-A76 Core Technical Reference Manual page 189

Configurations
Usage constraints
Accessing the CPUPWRCTLR_EL1
This syntax is encoded with the following settings in the instruction encoding:
Accessibility
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.
Traps and enables
c
The number of system counter ticks required before the core signals retention readiness on PACTIVE to the power controller. The core does not accept a retention
entry request until this time.
100798_0300_00_en
Encoding Number of counter ticks
010
011
100
101
110
111
There are no configuration notes.
This register can be read using MRS with the following syntax:
MRS <Xt>,<systemreg>
This register can be written using MSR with the following syntax:
MSR <systemreg>, <Xt>
This register is accessible in software as follows:
<systemreg>
S3_0_C15_C2_7
S3_0_C15_C2_7
S3_0_C15_C2_7
For a description of the prioritization of any generated exceptions, see Synchronous exception
prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture
®
profile for exceptions taken to AArch64 state.
Write access to this register from EL1 or EL2 depends on the value of bit[7] of ACTLR_EL2
and ACTLR_EL3.
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
Table B2-7 CPUPWRCTLR Retention Control Field (continued)
8
32
64
128
256
512
<systemreg>
S3_0_C15_C2_7 11
Control
E2H TGE
x x
x 0
x 1
reserved.
Non-Confidential
B2 AArch64 system registers
c
Minimum retention entry delay
(System counter at 50MHz-10MHz)
160ns-800ns
640ns – 3,200ns
1,280ns-6,400ns
2,560ns-12,800ns
5,120ns-25,600ns
10,240ns-51,200ns
op0 op1 CRn CRm op2
000 1111 0010
Accessibility
NS EL0 EL1 EL2
0 - RW n/a
1 - RW RW
1 - n/a RW
111
EL3
RW
RW
RW
B2-189