D9.41 Trcimspec0, Implementation Specific Register 0 - ARM Cortex-A76 Core Technical Reference Manual

D9.41 TRCIMSPEC0, Implementation Specific Register 0
The TRCIMSPEC0 shows the presence of any implementation specific features, and enables any features
that are provided.
Bit field descriptions
The TRCIMSPEC0 is a 32-bit register.
RES0, [31:4]
SUPPORT, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCIMSPEC0 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
No implementation specific extensions are supported.
0
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D9.41 TRCIMSPEC0, Implementation Specific Register 0

Figure D9-39 TRCIMSPEC0 bit assignments
reserved.
Non-Confidential
D9 ETM registers
4 3 0
SUPPORT
®
.
0x1C0
D9-551