D3.9 Edpidr1, External Debug Peripheral Identification Register 1 - ARM Cortex-A76 Core Technical Reference Manual

D3.9 EDPIDR1, External Debug Peripheral Identification Register 1
The EDPIDR1 provides information to identify an external debug component.
Bit field descriptions
The EDPIDR1 is a 32-bit register.
RES0, [31:8]
DES_0, [7:4]
Part_1, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The EDPIDR1 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Arm Limited. This is the least significant nibble of JEP106 ID code.
0xB
Most significant nibble of the debug part number.
0xD
Copyright © 2016–2018 Arm Limited or its affiliates. All rights

D3.9 EDPIDR1, External Debug Peripheral Identification Register 1

Figure D3-8 EDPIDR1 bit assignments
reserved.
Non-Confidential
D3 Memory-mapped debug registers
8 7 4 3
DES_0 Part_1
®
.
0xFE4
D3-427
0