ARM Cortex-A76 Core Technical Reference Manual page 251

LL1HvdRng, [11:8]
L1HvdBG, [7:4]
L1HvdFG, [3:0]
Configurations
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
100798_0300_00_en
L1 Harvard cache Range. Indicates the supported L1 cache maintenance range operations, for a
Harvard cache implementation:
Not supported.
0x0
L1 Harvard cache Background fetch. Indicates the supported L1 cache background prefetch
operations, for a Harvard cache implementation:
Not supported.
0x0
L1 Harvard cache Foreground fetch. Indicates the supported L1 cache foreground prefetch
operations, for a Harvard cache implementation:
Not supported.
0x0
Must be interpreted with ID_MMFR0_EL1, ID_MMFR1_EL1, ID_MMFR3_EL1, and
ID_MMFR4_EL1. See:
• B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1 on page
• B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1 on page
• B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 on page
• B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 on page
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
reserved.
Non-Confidential
B2 AArch64 system registers
B2-246.
B2-248.
B2-252.
B2-254.
®
B2-251