ARM Cortex-A76 Core Technical Reference Manual page 413

HMC, [13]
BAS, [12:5]
LSC, [4:3]
PAC, [2:1]
E, [0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
100798_0300_00_en
Higher mode control. Determines the debug perspective for deciding when a watchpoint debug
event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC
fields.
On Cold reset, the field reset value is architecturally
Byte address select. Each bit of this field selects whether a byte from within the word or double-
word addressed by DBGWVRn_EL1 is being watched. See the Arm
Manual Armv8, for Armv8-A architecture profile for more information.
Load/store access control. This field enables watchpoint matching on the type of access being
made. The possible values are:
Match instructions that load from a watchpoint address.
0b01
Match instructions that store to a watchpoint address.
0b10
Match instructions that load from or store to a watchpoint address.
0b11
All other values are reserved, but must behave as if the watchpoint is disabled. Software must
not rely on this property because the behavior of reserved values might change in a future
revision of the architecture.
Ignored if E is 0.
On Cold reset, the field reset value is architecturally
Privilege of access control. Determines the exception level or levels at which a watchpoint
debug event for watchpoint n is generated. This field must be interpreted along with the SSC
and HMCfields.
On Cold reset, the field reset value is architecturally
Enable watchpoint n. Possible values are:
Watchpoint disabled.
0
Watchpoint enabled.
1
On Cold reset, the field reset value is architecturally
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
reserved.
Non-Confidential
D2 AArch64 debug registers
.
Architecture Reference
®
.
.
.
®
D2-413