D6.9 Pmpidr2, Performance Monitors Peripheral Identification Register 2 - ARM Cortex-A76 Core Technical Reference Manual

D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2
The PMPIDR2 provides information to identify a Performance Monitor component.
Bit field descriptions
The PMPIDR2 is a 32-bit register.
RES0, [31:8]
Revision, [7:4]
JEDEC, [3]
DES_1, [2:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMPIDR2 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
r0p0.
0x0
RAO. Indicates a JEP106 identity code is used.
0b1
Arm Limited. This is the most significant nibble of JEP106 ID code.
0b011
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D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2

Figure D6-8 PMPIDR2 bit assignments
reserved.
Non-Confidential
D6 Memory-mapped PMU registers
8 7 4 3 2 0
Revision DES_1
JEDEC
®
.
0xFE8
D6-467