ARM Cortex-A76 Core Technical Reference Manual page 162

Ctype2, [5:3]
Ctype1, [2:0]
Configurations
100798_0300_00_en
Both per-core L2 and cluster L3 caches are present.
0b100
All other options.
0b000
If Ctype2 has a value of
0b000
Indicates the type of unified instruction and data caches at Level 2:
Either per-core L2 or cluster L2 cache is present.
0b100
All other options.
0b000
Indicates the type of cache implemented at L1:
Separate instruction and data caches at L1.
0b011
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the
Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile.
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B2.19 CLIDR_EL1, Cache Level ID Register, EL1
, then the value of Ctype3 must be ignored.
reserved.
Non-Confidential
B2 AArch64 system registers
B2-162