B2.74
ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
The ID_MMFR2_EL1 provides information about the implemented memory model and memory
management support in AArch32.
Bit field descriptions
ID_MMFR2_EL1 is a 32-bit register, and is part of the Identification registers functional group.
This register is Read Only.
HWAccFlg, [31:28]
WFIStall, [27:24]
MemBarr, [23:20]
UniTLB, [19:16]
HvdTLB, [15:12]
100798_0300_00_en
31
28 27
24 23
HWAccFlg
WFIStall
Hardware access flag. Indicates support for a hardware access flag, as part of the VMSAv7
implementation:
Not supported.
0x0
Wait For Interrupt Stall. Indicates the support for Wait For Interrupt (WFI) stalling:
Support for WFI stalling.
0x1
Memory Barrier. Indicates the supported CP15 memory barrier operations.
Supported CP15 memory barrier operations are:
0x2
•
Data Synchronization Barrier (DSB).
•
Instruction Synchronization Barrier (ISB).
•
Data Memory Barrier (DMB).
Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB
implementation.
Supported unified TLB maintenance operations are:
0x6
•
Invalidate all entries in the TLB.
•
Invalidate TLB entry by MVA.
•
Invalidate TLB entries by ASID match.
•
Invalidate instruction TLB and data TLB entries by MVA All ASID. This is a
shared unified TLB operation.
•
Invalidate Hyp mode unified TLB entry by MVA.
•
Invalidate entire Non-secure EL1 and EL0 unified TLB.
•
Invalidate entire Hyp mode unified TLB.
•
,
TLBIMVALIS
TLBIMVAALIS
•
,
TLBIIPAS2IS
Harvard TLB. Indicates the supported TLB maintenance operations, for a Harvard TLB
implementation:
Not supported.
0x0
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
20 19
16 15
MemBarr
UniTLB
HvdTLB
Figure B2-58 ID_MMFR2_EL1 bit assignments
,
TLBIMVALHIS
,
TLBIIPAS2LIS
TLBIIPAS2
reserved.
Non-Confidential
B2 AArch64 system registers
12 11
8 7
LL1HvdRng L1HvdBG
,
,
, and
TLBIMVAL
TLBIMVAAL
, and
.
TLBIIPAS2L
4 3
0
L1HvdFG
.
TLBIMVALH
B2-250
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