D9.44 Trcitiatbinr, Integration Instruction Atb In Register - ARM Cortex-A76 Core Technical Reference Manual

D9.44 TRCITIATBINR, Integration Instruction ATB In Register
The TRCITIATBINR reads the state of the input pins described in this section.
Bit field descriptions
The TRCITIATBINR is a 32-bit register.
For all non-reserved bits:
• When an input pin is LOW, the corresponding register bit is 0.
• When an input pin is HIGH, the corresponding register bit is 1.
• The TRCITIATBINR bit values always correspond to the physical state of the input pins.
[31:2]
AFVALIDM, [1]
ATREADYM, [0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCITIATBINR can be accessed through the external debug interface, offset
100798_0300_00_en
31
Reserved. Read undefined.
Returns the value of the AFVALIDMn input pin.
Returns the value of the ATREADYMn input pin.
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D9.44 TRCITIATBINR, Integration Instruction ATB In Register

Reserved
Figure D9-42 TRCITIATBINR bit assignments
reserved.
Non-Confidential
D9 ETM registers
2 1 0
AFVALIDM
ATREADYM
®
.
0xEF4
D9-554