ARM Cortex-A76 Core Technical Reference Manual page 181

B2 AArch64 system registers
B2.27 CPUPCR_EL3, CPU Private Control Register, EL3
Traps and enables
For a description of the prioritization of any generated exceptions, see Synchronous exception
prioritization in the Arm Architecture Reference Manual Armv8, for Armv8-A architecture
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