ARM Cortex-A76 Core Technical Reference Manual page 504

FRSYNCOVFLOW, [2]
IDLEACKOVERRIDE, [1]
AFREADYOVERRIDE, [0]
The TRCAUXCTLR can be accessed through the internal memory-mapped interface and the external
debug interface, offset
Configurations
100798_0300_00_en
Override SYNC packet insertion behavior. The possible values are:
SYNC packets are inserted into FIFO only when trace activity is low.
0
SYNC packets are inserted into FIFO irrespective of trace activity.
1
Force overflows to output synchronization packets. The possible values are:
No FIFO overflow when SYNC packets are delayed.
0
Forces FIFO overflow when SYNC packets are delayed.
1
When this bit is set to 1, the trace unit behavior deviates from architecturally-specified behavior.
Force ETM idle acknowledge. The possible values are:
ETM trace unit idle acknowledge is asserted only when the ETM trace unit is in idle
0
state.
ETM trace unit idle acknowledge is asserted irrespective of the ETM trace unit idle
1
state.
When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.
Force assertion of AFREADYM output. The possible values are:
ETM trace unit AFREADYM output is asserted only when the ETM trace unit is in
0
idle state or when all the trace bytes in FIFO before a flush request are output.
ETM trace unit AFREADYM output is always asserted HIGH.
1
When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior.
.
0x018
Available in all configurations.
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
D9.5 TRCAUXCTLR, Auxiliary Control Register
reserved.
Non-Confidential
D9 ETM registers
D9-504