D6.2 Pmcfgr, Performance Monitors Configuration Register - ARM Cortex-A76 Core Technical Reference Manual

D6.2 PMCFGR, Performance Monitors Configuration Register
The PMCFGR contains PMU specific configuration data.
Bit field descriptions
The PMCFGR is a 32-bit register.
RES0, [31:17]
EX, [16]
CCD, [15]
CC, [14]
Size, [13:8]
N, [7:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMCFGR can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Export supported. The value is:
Export is supported. PMCR_EL0.EX is read/write.
1
Cycle counter has pre-scale. The value is:
PMCR_EL0.D is read/write.
1
Dedicated cycle counter supported. The value is:
Dedicated cycle counter is supported.
1
Counter size. The value is:
64-bit counters.
0b111111
Number of event counters. The value is:
Six counters.
0x06
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D6.2 PMCFGR, Performance Monitors Configuration Register

17 16 15 14 13
Figure D6-1 PMCFGR bit assignments
reserved.
Non-Confidential
D6 Memory-mapped PMU registers
8 7
Size N
CC
CCD
EX
.
0xE00
0
®
D6-460