ARM Cortex-A76 Core Technical Reference Manual page 497

Offset Name
0x480
TRCACATRn
0x600
TRCCIDCVR0
0x640
TRCVMIDCVR0
0x680
TRCCIDCCTLR0
0x688 TRCVMIDCCTRL0 RW
0xEE4
TRCITATBIDR
0xEEC
TRCITIDATAR
0xEF4
TRCITIATBINR
0xEFC
TRCITIATBOUTR
0xF00
TRCITCTRL
0xFA0
TRCCLAIMSET
0xFA4
TRCCLAIMCLR
0xFA8 TRCDEVAFF0
0xFAC
TRCDEVAFF1
0xFB0
TRCLAR
0xFB4
TRCLSR
0xFB8
TRCAUTHSTATUS RO
0xFBC
TRCDEVARCH
0xFC8
TRCDEVID
0xFCC
TRCDEVTYPE
0xFE0
TRCPIDR0
0xFE4
TRCPIDR1
0xFE8
TRCPIDR2
0xFEC
TRCPIDR3
100798_0300_00_en
Type Reset Description
RW UNK D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7
on page D9-499
RW UNK D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0
on page D9-508
RW UNK D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0
on page D9-587
RW UNK D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
on page D9-507
UNK D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator
Control Register 0 on page D9-588
RW UNK D9.42 TRCITATBIDR, Integration ATB Identification Register
on page D9-552
WO UNK D9.46 TRCITIDATAR, Integration Instruction ATB Data Register
on page D9-556
RO UNK D9.44 TRCITIATBINR, Integration Instruction ATB In Register
on page D9-554
WO UNK D9.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
on page D9-555
RW D9.43 TRCITCTRL, Integration Mode Control Register on page D9-553
0x00000000
RW UNK D9.15 TRCCLAIMSET, Claim Tag Set Register on page D9-514
RW D9.14 TRCCLAIMCLR, Claim Tag Clear Register on page D9-513
0x00000000
RO UNK D9.21 TRCDEVAFF0, Device Affinity Register 0 on page D9-524
RO UNK D9.22 TRCDEVAFF1, Device Affinity Register 1 on page D9-526
WO UNK D9.47 TRCLAR, Software Lock Access Register on page D9-557
0x00000000
RO D9.48 TRCLSR, Software Lock Status Register on page D9-558
UNK D9.4 TRCAUTHSTATUS, Authentication Status Register
on page D9-502
0x47724A13
RO D9.23 TRCDEVARCH, Device Architecture Register on page D9-527
RO D9.24 TRCDEVID, Device ID Register on page D9-528
0x00000000
0x00000013
RO D9.25 TRCDEVTYPE, Device Type Register on page D9-529
RO D9.54 TRCPIDR0, ETM Peripheral Identification Register 0
0x0000000B
on page D9-564
RO D9.55 TRCPIDR1, ETM Peripheral Identification Register 1
0x000000BD
on page D9-565
RO D9.56 TRCPIDR2, ETM Peripheral Identification Register 2
0x0000000B
on page D9-566
RO D9.57 TRCPIDR3, ETM Peripheral Identification Register 3
0x00000000
on page D9-567
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
Table D9-1 ETM trace unit register summary (continued)
D9 ETM registers
D9.1 ETM register summary
D9-497