ARM Cortex-A76 Core Technical Reference Manual page 295

RES0, [1]
ED, [0]
Configurations
100798_0300_00_en
Uncorrected error recovery interrupt enable. When enabled, the error recovery interrupt is
generated for all detected Uncorrected errors that are not deferred. The possible values are:
Error recovery interrupt disabled.
0
Error recovery interrupt enabled.
1
Note
Applies to both reads and writes.
Reserved.
RES0
Error Detection and correction enable. The possible values are:
Error detection and correction disabled.
0
Error detection and correction enabled.
1
This register is accessible from the following registers when ERRSELR.SEL==0:
B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 on page
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B3.3 ERR0CTLR, Error Record Control Register
reserved.
Non-Confidential
B3 Error system registers
B2-199.
B3-295