D6.8 Pmpidr1, Performance Monitors Peripheral Identification Register 1 - ARM Cortex-A76 Core Technical Reference Manual

D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1
The PMPIDR1 provides information to identify a Performance Monitor component.
Bit field descriptions
The PMPIDR1 is a 32-bit register.
RES0, [31:8]
DES_0, [7:4]
Part_1, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The PMPIDR1 can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Arm Limited. This is the least significant nibble of JEP106 ID code.
0xB
Most significant nibble of the performance monitor part number.
0xD
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D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1

Figure D6-7 PMPIDR1 bit assignments
reserved.
Non-Confidential
D6 Memory-mapped PMU registers
8 7 4 3 0
DES_0 Part_1
®
.
0xFE4
D6-466