A5.1 About The Mmu - ARM Cortex-A76 Core Technical Reference Manual

A5.1 About the MMU
The Memory Management Unit (MMU) is responsible for translating addresses of code and data Virtual
Addresses (VA) to Physical Addresses (PAs) in the real system. The MMU also controls memory access
permissions, memory ordering, and cache policies for each region of memory.
A5.1.1 Main functions
The three main functions of the MMU are to:
• Control the table walk hardware that accesses translation tables in main memory.
• Translate Virtual Addresses (VAs) to Physical Addresses (PAs).
• Provide fine-grained memory system control through a set of virtual-to-physical address mappings
and memory attributes that are held in translation tables.
Each stage of address translation uses a set of address translations and associated memory properties that
are held in memory mapped tables called translation tables. Translation table entries can be cached into a
Translation Lookaside Buffer (TLB).
The following table describes the components included in the MMU.
Component
Instruction L1 TLB
Data L1 TLB
L2 TLB cache
Translation table prefetcher Detects access to contiguous translation tables and prefetches the next one. This prefetcher can be
The TLB entries contain either one or both of a global indicator and an Address Space Identifier (ASID)
to permit context switches without requiring the TLB to be invalidated.
The TLB entries contain a Virtual Machine Identifier (VMID) to permit virtual machine switches by the
hypervisor without requiring the TLB to be invalidated.
A5.1.2 AArch64 behavior
The Cortex-A76 core is an Armv8 compliant core that supports execution in AArch64 state.
The following table shows the AArch64 behavior.
AArch64
Address translation The Armv8 address translation system resembles an extension to the Long descriptor format address
system translation system to support the expanded virtual and physical address space.
Translation granule 4KB, 16KB, or 64KB for Armv8 Virtual Memory System Architecture (VMSA)
ASID size 8 or 16 bits depending on the value of TCR_ELx.AS.
VMID size 8 or 16 bits depending on the value of VTCR_EL2.VS.
PA size
Maximum 40 bits.
Any configuration of TCR_ELx.IPS over 40 bits is considered as 40 bits. You can enable or disable each
stage of the address translation independently.
100798_0300_00_en
Description
48 entries, fully associative.
48 entries, fully associative.
1280 entries, 5-way set associative.
disabled in the ECTLR register.
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Table A5-1 TLBs and TLB caches in the MMU
reserved.
Non-Confidential
A5 Memory Management Unit

A5.1 About the MMU

Table A5-2 AArch64 behavior
A5-62