D9.63 Trcseqrstevr, Sequencer Reset Control Register - ARM Cortex-A76 Core Technical Reference Manual

D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register
The TRCSEQRSTEVR resets the sequencer to state 0.
Bit field descriptions
The TRCSEQRSTEVR is a 32-bit register
RES0, [31:8]
RESETTYPE, [7]
RES0, [6:4]
RESETSEL, [3:0]
Bit fields and details not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The TRCSEQRSTEVR can be accessed through the external debug interface, offset
100798_0300_00_en
31
0
RES
Reserved.
RES0
Selects the resource type to move back to state 0:
Single selected resource.
0
Boolean combined resource pair.
1
Reserved.
RES0
Selects the resource number, based on the value of RESETTYPE:
When RESETTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by
bits[2:0].
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D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register

Figure D9-60 TRCSEQRSTEVR bit assignments
reserved.
Non-Confidential
D9 ETM registers
8 7 6 4 3
RESETSEL
RESETTYPE
.
0x118
0
®
D9-574